Design of an Arithmetic circuit using Verilog

module AND(x,y,z);
input x,y;
output z;
assign z = (x & y);
endmodule

module OR(x,y,z);
input x,y;
output z;
assign z = (x | y);
endmodule

module NOT(x,z);
input x;
output z;
assign z = ~x;
endmodule

module XOR(a,b,c);
input a,b;
output c;
wire w13,w14,w15,w16;
NOT not5(a,w13);
NOT not6(b,w14);
AND and5(a,w14,w15);
AND and6(b,w13,w16);
OR or5(w15,w16,c);
endmodule

module FA(X1,Y1,C1,S1,cout);
input X1,Y1,C1;
output S1,cout;
wire W1,W2,W3;
XOR xor1(X1,Y1,W1);
AND and7(X1,Y1,W2);
XOR xor2(W1,C1,S1);
AND and8(W1,C1,W3);
OR or6(W2,W3,cout);
endmodule

module arithmetic(cin,co,s1,s0,A1,B1,A2,B2,A3,B3,A4,B4,F1,F2,F3,F4);
input cin,s1,s0,A1,B1,A2,B2,A3,B3,A4,B4;
output F1,F2,F3,F4,co;
wire y1,y2,y3,y4,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,co1,co2,co3;
NOT not1(B1,w1);
AND and1(B1,s0,w2);
AND and2(w1,s1,w3);
OR or1(w2,w3,y1);
NOT not2(B2,w4);
AND and3(B2,s0,w5);
AND and4(w4,s1,w6);
OR or2(w5,w6,y2);
NOT not3(B3,w7);
AND and5(B3,s0,w8);
AND and6(w7,s1,w9);
OR or3(w8,w9,y3);
NOT not4(B4,w10);
AND and7(B4,s0,w11);
AND and8(w10,s1,w12);
OR or4(w11,w12,y4);
FA fa1(A1,y1,cin,F1,co1);   
FA fa2(A2,y2,co1,F2,co2);
FA fa3(A3,y3,co2,F3,co3);
FA fa4(A4,y4,co3,F4,co);
endmodule